About the job We are looking for digital design engineers to develop RTL code (Verilog/SystemVerilog) and participate in the creation of modern ASIC and microcontroller systems. 🛠️ Main responsibilities • Development of RTL modules in Verilog/SystemVerilog. • Simulation and analysis of functional blocks. • Integration of modules into a system-on-chip (SoC). • Setting up RTL simulators and design verification. • Process automation (make, Python/Perl/TCL/Shell). • Creation of testbenches and documentation. • Working with version control systems (Git, SVN). ✅ Requirements • Experience in Verilog development (VHDL is welcome). • Knowledge of interfaces: UART, I2C, SPI, CAN, USB, MIPI, SATA, etc. • Experience with IDEs: Vivado, Xilinx ISE, Cadence Genus/Incisive/Xcelium. • Microcontroller system debugging skills (GDB, OpenOCD). • Proficiency in Linux/Windows, version control systems. • English for reading documentation and correspondence. 💼 Conditions • Work primarily in the office (Class A building, Rumyantsevo metro station). • Flexible schedule: the ability to choose a convenient start and end of the working day. • Fixed salary.